In semiconductor fabrication processes, a single layer of features is sometimes formed by using multiple-exposure or multiple-patterning technology to improve a spatial resolution of the layer. For example, if a layer of features is to be fabricated using N exposure or patterning processes (i.e., N-exposure or N-patterning), N being a positive integer no less than 2, layout patterns corresponding to a layout design for the layer of features are assigned to N different groups for corresponding exposure or patterning processes. The pattern-assigning process is sometimes performed in a manner similar to resolving a coloring problem under graph theory. Therefore, the pattern-assigning process is sometimes referred to as a “coloring process,” and a layout design is sometimes referred to as “N-colorable” if layout patterns of the layout design are capable of being assigned to N different patterning groups. Performance of a pattern-assigning process for a layout design is usually computational resource demanding and time consuming.